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P8X Card Design Standards

Applies to every plug-in card (control, register bank, ALU, memory, I/O, CF-IDE, PS/2, the bus test card, and future cards). The backplane has its own design notes and is explicitly out of scope here. When a card deviates from a rule, the deviation and its reason go in that card's schematic notes — silent exceptions are bugs.

Memory card rev D was the reference implementation of these standards in the Eagle flow; since 2026-09-18 the boards are generated in KiCad, with the rev F memory card as the reference (hardware/KICAD-BOARDS.md).

1. Mechanical

Item Standard
Board size 280 × 140 mm, 1.6 mm thickness — the uniform KiCad card size since 2026-09-18 (first planned as a 160 × 100 mm Eurocard); the 140 mm connector edge leaves room beyond the ~94 mm DIN 41612
Connector DIN 41612, 3-row 96-pin male, right-angle, on the left board edge as laid out in KiCad; status LEDs on the opposite edge
Connector placement Pin row spans y = 10.16–88.90 mm; row A nearest board surface — VERIFY against mated orientation before first fab and then freeze the footprint
Component height ≤ 20 mm (planned for a 1" slot pitch; the KiCad backplane's pitch is 28 mm); nothing on the back side except pin protrusion
Card extraction Leave 5 mm strip at the front edge (opposite the connector) free of components for a puller/handle; card name visible there
Mounting No card-level mounting holes required; front strip may take an ejector later — keep it clear

2. Stackup & Layout

Item Standard
Layers 4: Top = signal, In1 = solid GND plane, In2 = solid +5V plane, Bottom = signal (Eagle layer setup 1*2*15*16)
Planes Never split, never route on. Power distribution is the planes, period
Signal traces 0.4 mm width, 0.3 mm minimum clearance
Bus entry Backplane signals fan out from the connector on Top where possible; keep bus stubs short (< 25 mm from connector pad to first IC pin)
Clock CLK routed first, shortest practical path, no stubs to chips that don't use it
Vias 0.8 mm pad / 0.4 mm drill standard

3. Power & Decoupling

  • 100 nF ceramic per IC, placed within 5 mm of its VCC pin, via straight to both planes
  • One 10 µF bulk per card near the connector power pins
  • Power pins per rev C/D bus: +5V = A1, B1, C1, A2, B2, C2; GND = A31, B31, C31, A32, B32, C32, plus the odd row-B guard pins B3, B5, …, B25 (stitch these straight into the GND plane). Do NOT stitch B4, B6, …, B26 — those are spare bus lines SPARE12–SPARE23 — nor B27–B30 (CLRC/BSEL/IRQ/SPARE11), which are signals.
  • Budget: declare expected current draw on the schematic title block (rule of thumb ~20 mA per HCT IC average, more for LS or anything driving LEDs)

4. Logic Family & Unused Pins

  • Default family 74HCT (TTL-compatible thresholds, low power). Mixing in 74LS/74F is allowed only for speed-critical paths and must be noted
  • Unused CMOS inputs are never left floating — tie to GND (or VCC where logic demands). This includes unused gates in a package
  • Unused outputs: leave open, mark with no-connect intent in the schematic (KiCad: NC flag; Eagle: accept the ERC warning, list the pins in a schematic note)
  • Every pin on the schematic must be accounted for: netted, tied, or explicitly NC. The generators enforce this mechanically — keep that property

5. Bus Interface Rules (the constitution of this machine)

  1. Drive the data bus only through a tri-state buffer/transceiver enabled by this card's decoded DOE code. Never from a bare output
  2. Field decoding is per-card: each card carries its own decoder(s) for the DOE/DLD codes assigned to it (74138/74154). Codes are allocated in the bus pinout document; a card uses only its assigned codes
  3. Loads happen on the rising CLK edge when the card's DLD code is present. Write-type strobes (memory, I/O latches) are gated with CLK̄ so address/data settle in the first half-cycle and strobe in the second — copy the memory card's WE̅ circuit
  4. The address bus is input-only to every card except the register bank
  5. Never add pull-ups/pull-downs to backplane signals on a card — bus conditioning (D0–D7 pull-ups, clock termination) lives on the backplane only, exactly once
  6. Control signals a card doesn't use: leave the connector pin unconnected (NC), never tie a bus signal to a rail on a card

6. Address Decoding (memory-mapped cards)

  • I/O page is $FF00–$FFFF; detect with 8-input NAND on A8–A15 (the memory card's 7430 pattern). Sub-decode with a 74138
  • I/O address allocations are recorded in the bus pinout document before a card is built — no squatting
  • Any card asserting data onto the bus for a read must qualify on (its address decode) ∧ (DOE = MEM)

7. Schematic & Naming Conventions

  • Net names match the bus pinout document exactly (D0–D7, A0–A15, DOE0–3, DLD0–3, PSEL0–1, PINC, PDEC, CLK, CLKB, -RES, LDF, ALUS0–3, ALUM, CIN, SH0–1, SPARE4–23). Active-low signals are prefixed with a dash (e.g. -RES, -RD, -MEMW)
  • Reference designators: U = ICs, J = connectors, C = caps, R/RN = resistors/ networks, D/LED as usual. J1 is always the bus connector
  • Card value/title block carries: card name, rev letter, date, expected current, and deviations from this document
  • One generator script per card is the canonical netlist; the CAD files are artifacts of it. A netlist change means regenerate, never hand-edit copper against an stale netlist

8. Silkscreen

  • Card name + rev, large, on the front-edge strip (readable with card installed)
  • Pin 1 markers on every IC; connector A1/C32 corners labeled
  • Designators readable after assembly (not under sockets)

9. Status LEDs (required on every card)

  • PWR LED (green): top-right corner of the card, 1 kΩ from +5V, LED to GND. Visible with the card installed
  • SEL LED (yellow): directly below the PWR LED. Lights whenever the card is selected — defined per card as the union of its decoded DOE/DLD codes (and address decode for memory-mapped cards). A card may instead provide a finer-grained LED set whose union covers SEL's meaning — the memory card does this with four: ROM access, RAM access, read cycle, write cycle. Select-type LEDs must gate raw chip-select/address decode with the bus-access qualifier (e.g. -BOE) so they indicate real accesses, not idle address-bus residue
  • Drive rules: never hang an LED directly on a bus or decoded control net — buffer it through a spare gate (which cards have anyway; this is the approved exception to the tie-unused-inputs-to-GND rule: a repurposed gate's inputs go to the signal instead). Sink configuration: +5V → 1 kΩ → LED → gate output; lights when the buffered active-low select is low
  • Brightness semantics: at full speed the SEL LED's brightness is duty cycle — it reads as an activity meter. At single-step it's a static "this card is on the bus this microcycle" indicator, which is the debugging payoff. If single-pulse visibility at full speed is ever wanted, a pulse stretcher (RC + transistor or 74123) may be added per card; note it as a deviation

10. Assembly & Test Provisions

  • All ICs socketed (machined-pin) — this is a hobby machine; chips will be swapped and probed for years
  • Test points (loop or pad) on: card-local decoded strobes (e.g. RD_N, MEMW_N equivalents), and any card-internal clock or state line you'd want a scope on at 2 a.m.
  • Every card must be safe to insert alone with only the control card present: no card may require another card (other than control) to avoid bus contention or undefined drive
  • Bring-up note on each schematic: the one-line test that proves the card alive (memory card example: "monitor reads $FF17, RDY set")

11. Fab Checklist (per card, before Gerbers)

  • [ ] Pour planes, run DRC clean at 0.3/0.4 rules
  • [ ] Zero airwires
  • [ ] Connector footprint verified against physical part (orientation!)
  • [ ] Every pin netted/tied/NC-accounted
  • [ ] Decoupling count = IC count
  • [ ] Silkscreen: name, rev, pin-1 marks
  • [ ] PWR + SEL LEDs present, top-right, buffered per section 9
  • [ ] Gerber + drill reviewed in an independent viewer