hardware/¶
The physical machine: one passive backplane, six plug-in CPU cards, a PS/2 input
card, and a bus test card for bring-up. Each board has its own directory holding a
chip-by-chip README, a theory of operation or design doc, and the KiCad board
(kicad/: the .kicad_pcb, the Freerouting session, orderable Gerbers, a
placement PDF and renders). Every board is designed and routed; none has been
fabricated yet. Board status: KICAD-BOARDS.md; build
readiness against the emulator and the FPGA: RECONCILIATION.md.
| Board | Directory | Function |
|---|---|---|
| Control / Microcode | control-card/ | Clock, reset, sequencer, microcode EPROMs, IR, condition mux, front panel |
| Register Bank | regbank-card/ | P0–P3 16-bit pointer registers, address-bus drivers |
| ALU | alu-card/ | A/B/T/T2 registers, 74181 ALU, shifter, FLAGS |
| Memory | memory-card/ | 28C256 ROM (6 KB window, $0000–$17FF) + 2× 62256 SRAM, address decode (rev F) |
| I/O | io-card/ | Switches, LEDs, bus monitor, two 6850 ACIAs ($FF04/05, $FF08/09) with two DB9s (rev B) |
| CF-IDE | cf-card/ | Two CompactFlash drives in 8-bit True IDE mode: $FF10–$FF17 and $FF18–$FF1F (rev B) |
| PS/2 | ps2-card/ | Keyboard + mouse at $FF58–$FF5F: an ATmega1284P behind a latch bridge (rev A) |
| Bus test | bustest-card/ | Bring-up tool: a Raspberry Pi Pico drives the bus over USB, one microcycle at a time |
| Backplane | backplane/ | 8-slot passive 96-pin DIN 41612 bus (rev C2), 262 × 128 mm |
The plug-in cards are all 280 × 140 mm, 4-layer (signals on the outer layers, GND and +5 V planes inside).
Eagle (frozen). The first board generation was drawn in Eagle/Fusion from
generators/gen_eagle.py. On 2026-09-18 the KiCad flow replaced it: each board's
Eagle .sch/.brd and its schematic and placement PDFs moved to
<board>/eagle-deprecated/, frozen at rev E, and are no longer maintained (the
Eagle memory card still carries the old 8 KB ROM decode; the KiCad rev F board has
the 6 KB one). gen_eagle.py stays the source of the netlists.
Deprecated: the standalone LED test card (a write-only 8-LED output latch that decoded
$FF0C) was a CAD-workflow trial, never built. It has been moved todeprecated/led-card/and its I/O address$FF0Cis now free. (This is unrelated to the$FF02LED latch the emulator traces, which stays.) The combined I/O + CF + PS/2 peripheral card is parked inparked/peripheral-card/(2026-09-19); the design went back to three cards.
Not yet realised as TTL boards¶
See RECONCILIATION.md for the full board-vs-emulator/FPGA build-readiness pass. Subsystems the emulator and/or the FPGA already provide that have no TTL card yet:
| Subsystem | Where it lives now | TTL board |
|---|---|---|
MDU multiply/divide ($FF30–$FF3F) |
emulator model + FPGA (mdu_core.v) |
none yet |
Graphics-language port ($FF50–$FF54) |
emulator model + the Tang Nano 20K graphics card | none (the FPGA card is the graphics engine) |
IRQ controller ($FF06 device-IRQ model) |
emulator model | none yet — the next card to design |
p8x-bom.csv — the orderable bill of materials for the whole machine
(ICs, sockets, connectors, passives), generated by
../generators/gen_bom.py.
Rebuilding boards¶
Generators are canon — never hand-edit a .kicad_pcb. The netlists live in
../generators/gen_eagle.py (CARDS, busnet());
gen_kicad.py turns a card into a placed KiCad board (the memory, I/O, CF, PS/2
cards and the backplane have bespoke placement scripts in their kicad/
directories), Freerouting routes it, and check_card.sh runs the readiness check
(ERC, gate-level simulation where a testbench exists, DRC, mounting-hole keepout,
fab minimums). One command does all of it, from the repository root:
sh generators/build.sh memory-card # one board (or: all)
sh generators/check_card.sh memory-card # the readiness check alone
It needs KiCad 10 and a Freerouting jar. See ../generators/README.md for the scripts and ../docs/p8x-card-standards.md for the rules every card follows.